TC94A48FG Datasheet | Toshiba

Features - - - Incorporates a 1-bit Σ-∆ AD converter (2 channels). THD+N: -78 d B (typ.), S/N ratio: 92 d B (typ.) Incorporates a multi-bit Σ-∆ DA converter (6 channels). THD+N: -88 d B (typ.), S/N ratio: 98 d B (typ.) Digital input/output ports Four input ports (8 channels) Four output ports (8 channels) The DSP block specifications are as follows: Data bus : 24 bits M ultiplier/adder : 24 bits × 24 bits + 51 bits → 51 bits Accumulator : 51 bits (sign extension: 4 bits) Program ROM : 3072 words × 16 bits Program RAM : 1024 words × 16 bits XRAM : 4096 words × 24 bits YRAM : 1024 words × 24 bits CROM : 1024 words × 24 bits The microcontroller interface can be selected between serial mode and I2C bus mode. Operating supply voltage: 3.3 V (some pins accept 5 V) CMOS silicon structure supports high speed. The package is a 64-pin LQFP (0.5-mm pitch) package. P-LQFP64-1010-0.50E Weight: 0.4 g (typ.) - - - - - 1 2005-09-28 http://.. Block Diagram 11.2896MHz(256fs) LRCKO /MIACK /MIDIO MCKO GPO1 GPO0 BCKO /MICS /MICK MIMD GPI1 GPI0 MILP PLLC ＰＬＬ Timing Generalperpose port Microcontroller interface /RST BTMD LRCKI0 LRCKI1 BCKI0 BCKI1 SDI0 SDI1 SDI2 SDI3 (8ch) SDO0 ＳＯ SDO1 SDO2 ＳＩ (8ch) 16bit Instruction DSP ΣΔ ΣΔ ＤＡＣ １ｃｈ ＤＡＣ ２ｃｈ ＤＡＣ ３ｃｈ VREF ΣΔ ΣΔ ΣΔ ＤＡＣ ４ｃｈ ＤＡＣ ５ｃｈ ＤＡＣ ６ｃｈ SDO3 DAO1 DAO2 LIN ADVL ADVR ＡＤＣ Ｌｃｈ ＭＡＦ( →4fs) (4fs ra te × 6ch) (4fs ra te ×2ch) ΣΔ DAO3 VRI VREF VREF REG Buffer (64w ×21b) (4fs ra te ×6ch) (4fs ra te ×...